PCB – part 2 of X Clock distribution and impedance control


So, it’s time for a second post in this series of tips and tricks for PCB designers. The goal is to cover some common areas of challenges that engineers or DIYers might come across.

Most digital boards have at least one high speed signal. And in many cases this is a clock signal. A clock signal is also in many cases distributed to more than one IC. And this is actually what this post is about. What should we think about and how can we design high speed digital signal distributions? The RF designer might say that you should always have the correct impedance at the source, transmission lines and correct termination of the signal at its receiver. Or you might get the answer to use balanced signaling with correct source impedance, transmission lines and termination resistors. But you have single ended CMOS signals! And you also might have one source with two or more receivers. Either you give up and just connect the clock source to the receivers and hope for the best or you start reading…

Before I present any solutions, I have to emphasize the importance of using ground planes as soon as there are any high speed signals on the board. A low impedance solid or X-hatched ground plane is really needed to get in control over the signal integrity of the board. A typical board stackup consist of two signaling layers on the outer layers and a core with ground and power planes. With a good component placement, 4-layers are really enough for the majority of circuit boards. If we do a great job in board sectioning, GPIO-pinout and component placement, even many complex board layouts can be solved with only 4 layers and good signal integrity. Of course with manual routing.

But you might run into signal integrity issues even with a solid ground plane, and no issues with ground bounce (described in my previous post). Clock distribution is often a source for signal integrity problems. Just look at the figure below. This is a simple simulation that intends to be quite close to the real world.


In the simulation a clock (tr/tf 1ns) is distributed to two receivers. The source impendance is set to 25 ohms (quite typical). The impedance of the clock signal is 100 ohms. 100 ohms is about the typical impedance you will have on a 1.6 mm, 4- layer standard FR4 board with 6-8mil signal width and ground/power planes in the middle. The red signal length in this example is 40 mm long and the blue is 120 mm. And we really have a signal integrity problem here. We also see some clock skew, but the real problem is ringing caused by reflections.

However, there is a very simple solution to this. Just add a 47 ohm resistor as close to the source as possible – one damping resistor for each clock path. And this is what the signals will look like. No problems what so ever with signal integrity and no termination resistors or changes in the board specification.

wdampingToday’s tips:

  • Damping resistors are good for signal integrity issues
  • Avoid stubs (good routing)
  • Avoid sharp 90deg edges on routing
  • RF is not covered in this post…


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